Advanced Architecture Optimizes the Atmel AVR CPU

 

Delivering High Performance and Low Power—With Small Code

Based on the Harvard Architecture
The high performance and low power consumption of the AVR microcontrollers is no accident, but a result of a hard work and patented technology. Atmel’s 8- and 32-bit AVR CPUs are based on an advanced Harvard architecture that is tuned for power consumption and performance. Like every Harvard architecture device, the AVR CPU has two busses: one instruction bus where the CPU reads executable instructions; and one data bus to read or write the corresponding data. This ensures that a new instruction can be executed in every clock cycle, which eliminates wait states when no instruction is ready to be executed.

The busses in AVR microcontrollers are configured to provide the CPU instruction bus priority access to the on-chip Flash memory. The CPU data bus has priority access to the SRAM.

 

Reducing Complexity, Increasing Efficiency

CPU-AVRMany people believe RISC is an acronym for "Reduced Instruction Set Computer", and that a RISC device must have a limited number of instructions. But those familiar with the history RISC and CISC will know that RISC is an acronym for "Reduced COMPLEXITY Instruction Set Computer". Since the term RCISC was inelegant, the acronym RISC was applied to the theory.

The Atmel AVR does not necessarily reduce the number of instructions in the set, but reduces the complexity of the digital circuitry required to decode each instruction. Since every instruction is a multiple of 16 bits, no energy is wasted trying to transfer and decode bits that contain no useful information.

To make the AVR instruction set as efficient as possible, the Atmel team behind the AVR CPU invited compiler experts from IAR Systems to co-develop the first AVR C compiler. Following extensive refinement, the AVR architecture became optimized for C-code execution, with bottlenecks completely eliminated during the construction phase. That is why the AVR has become synonymous with small code size, high performance, and low power consumption.

 

Enhancing Access with Working Registers

Usually, when the CPU executes a program, it requires frequent access to a limited set of data, including pointers, loop counters, semaphore status bits, and array indexes. In fact, close inspection of source code will reveal that most of the data is only required for a very short amount of time, then later discarded. That is why the AVR CPU contains multiple "working registers," which store dynamic data inside the CPU. Organized in a "register file," they eliminate the need to move temporary data from CPU to SRAM—only to read it back a few cycles later. The register file is extremely fast, allowing the CPU to read, execute, and store the result back into a register in a single clock cycle. They also require far less energy when accessed, compared to accessing a large SRAM with long address and data lines. Because no cycles are wasted, power consumption for executing code is greatly reduced.

 

DSP Instructions

The 32-bit AVR contains a very wide instruction set—with integer, fixed point and floating point DSP instructions—giving it the highest CPU performance of any AVR CPU. The 32-bit AVR instruction set includes saturation and rounding instructions that help speed up loops by requiring no internal range check of intermediate results. With fast multiply, accumulate, and divide instructions, the 32-bit AVR is the perfect choice for applications that require extensive digital signal processing.