AVR32 32-bit MCU - AP7000

Application Processors for Compute-intensive Embedded Control

The AP7000 is the first AVR32-based processor family and the first to integrate on a single chip, virtually all the functionalities required for multimedia systems deployed in cell phones, digital cameras, PDAs, automotive infotainment, set top boxes, and home entertainment systems, as well as network switches/routers and printers.

Vector Multiplication Co-processor

Connectivity

The AT32AP700x family is available now.

Vector Multiplication Co-processor

Multimedia applications commonly require arithmetic operations on 3x8-bit matrices for image filtering (FIR filtering), image color-space conversion (RBG<->YUV), image scaling, and MPEG-4 Quarter Pixel Motion Estimation. In order to keep CPU throughput as high as possible, the AP7000 has integrated the vector multiplication unit (VMU) to the AVR32 AP co-processor interface, tightly coupled to the CPU.
For example, MPEG4 video is compressed using the YUV color space, while most video DACs and LCD controllers require RGB input. The vector multiplier co-processor executes this conversion in real-time without CPU intervention. When used for image scaling operations, the AP7000’s vector multiplication co-processor increases the performance by as much as ten times.

Direct Memory Access (DMA)

Managing data-intensive applications with streams of data passing between the peripherals and the memories can seriously compromise the CPU. Without DMA, the 100 Mbps Ethernet MACBs and the 480 Mbps USB slave controller would take up all the CPUs cycles. The AP7000 provides several flexible Direct Memory Access (DMA) mechanisms that offload, from the CPU, data transfers between peripherals and memory and between two memory locations in the chip. Two simultaneous memory-to-memory data transfers can be performed between on-chip SRAM, or off-chip memories connected to the chip's external bus interface (EBI), as they are all addressable to the DMA controller.

Dynamic Frequency Scaling of Four Clock Domains

The AP7000 architecture has a multi-layer, high-speed bus architecture that increases performance by allowing multiple operations to take place in parallel. In addition, there are two peripheral bus bridges that allow different clock frequencies to be set for high- and low-speed peripherals. In a conventional bus structure, the bus clock is determined by the fastest peripheral, such that slower peripherals that could operate on a slower bus, draw unnecessary power. The AP7000 allows the dynamic configuration of the individual clock frequencies of these two bridges, as well as the frequency of the CPU's internal clock and that of the bus matrix. Dynamic frequency scaling algorithms are used to set the clocks in each of the four domains at the lowest possible frequency for the function it is performing.