AVR32 32-bit MCU - UC3A Series

The World's Lowest Power 32-bit Flash MCU with Ethernet and USB On-The-Go

80 Dhrystone MIPS and Draws Only 40 mA at 66 MHz

The AVR®32 UC3A Series – based on Atmel® AVR32 UC core – feature a 512K bytes Flash, an embedded 10/100 Ethernet MAC, a full-speed (12 Mbps) USB 2.0 with on-the-go (OTG) capability and an SRAM/SDRAM external bus interface.

The AT32UC3A0512 and AT32UC3A1512, the first devices available, deliver 80 Dhrystone MIPS (DMIPS) at 66 MHz and consume only 40 mA at 3.3V. The power consumption, as low as 1.65 mW/DMIPS, outperforms by a ratio of 1.7 to 4.3 other available architectures offering similar feature sets and lower processing performances. The standby power consumption of UC3A Series is just 40 micro-Amps.

The AVR32 UC core is the second core to be based on Atmel's AVR32 architecture, la unched in 2006. It has single cycle DSP instructions that include multipliers and multiply-and-accumulate, and executes 1.3 DMIPS/MHz.

Dual-bank pipelined Flash delivers single-cycle instructions – In contrast to other MCUs, the AVR32 UC core, system bus matrix, memory subsystem and peripherals were designed from the ground up, as a whole, to ensure optimum performance. The AVR32 UC core was designed specifically to interface to on-chip Flash memories. The Flash on UC3A Series devices uses a pipelined, dual-bank architecture that outputs one word every clock cycle when executing sequential code, with or without a wait state. Employing a wait-state allows microcontrollers clock frequency to be increased from 40 MHz to 66 MHz, and results in a negligible reduction in per cycle throughput of only 8% - from1.3 to 1.2 DMIPS/MHz.

Six Layer Bus Architecture with Dynamic Frequency Scaling – UC3A Series MCUs have a six-layer high speed bus matrix with point-to-point connections from all masters to all slaves, enabling masters to concurrently access any slave at a maximum speed of 264M bytes per second at 66 MHz. If multiple masters wish to access the same slave, arbitration is automatically performed. The bus masters in UC3A Series devices are the AVR32 UC core data and instruction interfaces, peripheral DMA controller, and several high speed peripherals such as the Ethernet MAC and USB. The bus slaves are the on-chip SRAM and Flash memories, USB, the two peripheral bus bridges, and the external bus interface (EBI).

Peripheral DMA Controller Ensures up to 24M bytes per Second Data Transfer at 66 MHz – The 15 channel peripheral DMA controller on the UC3A Series connects each peripheral directly to the entire addressable memory system, enabling high bandwidth data transfers without any processor overhead. Conventional processors, which require the CPU to transfer data one byte at a time, consume 55% of their processing resources at just 250K bytes/s and 100% of it at 500K bytes/s. The peripheral DMA on UC3A Series MCUs provides 15 DMA channels with a total available bandwidth of 24M bytes/s.

Peripheral Set Matches that of Atmel's ARM-based Controllers – The UC3A Series MCU family utilizes many of the same features Atmel developed for its SAM7 and SAM9 families of ARM-based MCUs including the peripheral DMA controller, multi-layer high speed bus architecture, Ethernet MAC, analog to digital converter and serial communication peripherals.

1 0/100-Mbps IEEE 802.3-compliant Ethernet (MAC) – Configurable in full- or half-duplex modes, the UC3A Series' Ethernet MAC has dedicated DMA, a programmable interpacket gap, support for virtual-LAN tagged frames and automatic-pause frame generation and termination. A dual mode interface offers a seamless Media Independent Interface (MII) with a large selection of PHYs for Fast Ethernet applications, or a Reduced Media Independent Interface (RMII) which uses less I/O.

USB OTG – A full speed (12 Mbps) USB 2.0 device with On-The-Go (OTG) capability has dedicated DMA, can interface to a personal computer as a device, and can behave as a USB host to support small USB devices such as USB Flash keys, printers, keyboards or mice. The USB device has a dedicated memory that supports seven software configurable end-points so several USB classes can run simultaneously.

Communications interfaces include two master/slave serial parallel interfaces (SPIs), one synchronous serial controller (SSC), one master/slave two-wire interface (I2C compatible) and four USARTs with hardware flow-control. One USART has special extensions to support modem, IrDA and smart-card ISO7816 serial protocols.

UC3A Series microcontrollers are available with an external bus interface (EBI) that extends the addressable physical memory to 16M bytes. Its non-multiplexed 16-bit data bus can interface to high density external SRAM, SDRAM, ROM, Flash devices and memory-mapped devices such as LCDs or FPGAs.

Devices have three 16-bit timers and seven pulse width modulators (PWM) that can trigger the 10-bit 8-channel ADC to ease electrical motor control design.

On-chip System Manager – The on-chip system manager includes an internal voltage regulator for 3.3V single power supply operation, power-on reset, brown-out detector, hardware watchdog timer and a real-time timer. The clock system provides an on-chip RC oscillator, 2 high frequency external oscillators, one 32 kHz oscillator and two independent on-chip PLLs. Special security options are available to protect Flash content from being corrupted by the application itself or from being read from external unauthorized access.

Consumes 40 µA in Sleep Mode and 600 µA/MHz in active – The compact nature of the AVR32 UC instruction set and the tight coupling of the memories to the processor minimizes the number of power-consuming memory accesses. In addition, two separate peripheral bus bridges allow different clock frequencies to be set for high- and low-speed peripherals, so slower peripherals can operate on a slower bus that draws less power. The frequencies of the two bus bridges and the CPU clock can be individually and dynamically configured to the lowest possible frequency that allows the system to operate. Individual clocks can also be completely switched off.

Any section of the UC3A device that is not in use can be switched off by disabling its clock. The UC3 core uses a multi-threshold transistor library to reduce static power consumption.

UC3A Series standby power consumption is just 40 µA (ambient temperature), and operating power consumption is 40 mA at 66 MHz with all clocks active (600 µA/MHz).