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Field Programmable Gate Array

The Atmel AT40KAL Series co-processor FPGAs range from 5K to 50K usable gates and are designed for high-density, compute-intensive DSP and other fast logic designs. The AT40KAL family solves the Logic vs. SRAM trade-off problem by providing fast, flexible, distributed 10 ns FreeRAM™ without using valuable logic resources. Structured logic functions, including variable array multipliers, can be implemented directly in core cells without using any bussing resources, providing dramatic improvements in speed, utilization, power and system cost. Atmel FPGA technology is now available as an embedded core. The first family of products based on this technology is the FPSLIC™ family. FPSLIC (Field Programmable System Level Integrated Circuits) devices combine 5 - 50K of AT40KAL FPGA with up to 36K of SRAM and a 25 MHz AVR MCU.

The AT40KAL family are FPGAs with the ability to implement Cache Logic design, where part of the FPGA can be reprogrammed without loss of register data, while the remainder of the FPGA continues to operate without disruption. This is ideal for building adaptive filters, variable coefficient multipliers and other designs where the datapath can change to increase system performance.

The Atmel Mature AT6000 Series FPGAs as well as the AT40K [5V version] are designed to speed up processor-based system performance while lowering power, part count and cost. The massive register counts (1,024 to 6,400 registers) make them ideal for use as re-configurable DSP co-processors.

All Atmel FPGAs can be designed using industry-standard EDA tools such as Mentor’s Precision Synthesis for VHDL and Verilog on a PC platform. Atmel offers an Integrated Development System [IDS] software that enables place and Route while enabling Designers to synthesize their designs using Industry standard Synthesis tools.

Atmel has a family of FPGA Serial Configuration EEPROMs in densities ranging from 256 K to 32 Mb. This unique family of products offers in-system reprogrammability, as well as the ability to program using a standard programmer. Now, not only is the FPGA reprogrammable in-system; so is the configuration memory.

Devices

Device Family Summary Benefit Applications Technologies Key Parameters

Speed up processor-based system performance while lowering power, part count and cost.

 Massive register counts (1,024 to 6,400 registers) make them ideal for use as re-configurable DSP co-processors.

 

5k to 40k Gates

5V

Fast, flexible, distributed 10 ns FreeRAM™ without using valuable logic resources

High-density, compute-intensive DSP and other fast logic designs

 

5k to 50k Gates

3V