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The AT40KAL family are FPGAs with the ability to implement Cache Logic design, where part of the FPGA can be reprogrammed without loss of register data, while the remainder of the FPGA continues to operate without disruption. This is ideal for building adaptive filters, variable coefficient multipliers and other designs where the datapath can change to increase system performance.

 
Device
Description

5K - 10K Gate Coprocessor FPGA with FreeRAM, Enhanced Performance Improvement, and Bi-Directional I/Os (3.3V)

10K - 20K Gate Coprocessor FPGA with FreeRAM, Enhanced Performance Improvement, and Bi-Directional I/Os (3.3V)

20K - 30K Gate Coprocessor FPGA with FreeRAM, Enhanced Performance Improvement, and Bi-Directional I/Os (3.3V)

40K - 50K Gate Coprocessor FPGA with FreeRAM, Enhanced Performance Improvement, and Bi-Directional I/Os (3.3V)