Iniciando

Informaremos tudo o que você precisa saber para começar a avaliar e trabalhar com este produto.

Itens relacionados




Datasheet

PDF

Software

Descrição

5962-01B01 (for MH1 and MH1RT series)

5962-01B01 (for MH1 and MH1RT series) Standard Microcircuit Drawing

(tamanho do arquivo: 435261, 64 páginas, atualizado: 1/07)

5962-08B01 (for MH1 and MH1RT series) Standard Microcircuit Drawing

5962-08B01 (for MH1 and MH1RT series) Standard Microcircuit Drawing Complete

(tamanho do arquivo: 143032, 22 páginas, revisão C, atualizado: 7/10)

5V Compliant Buffers with Core Powered AT 2.5V

5V Compliant Buffers with Core Powered AT 2.5V Errata

(tamanho do arquivo: 109773, 13 páginas, revisão A, atualizado: 4/09)

5V Compliant Buffers with Core Powered AT 2.5V Errata Sheet

9202-076 ESCC Detail Specification

9202-076 ESCC Detail Specification Complete

(tamanho do arquivo: 855082, 34 páginas, revisão 4, atualizado: 11/10)

This specification details the ratings, physical and electrical characteristics and test and inspection data for the component type variants and/or the range of components specified below. It supplements the requirements of, and shall be read in conjunction with, the ESCC Generic Specification listed under Applicable Documents.

LVDS in MH1RT technology

LVDS in MH1RT technology Errata

(tamanho do arquivo: 351581, 8 páginas, revisão A, atualizado: 10/10)

LVDS in MH1RT Technology

MH1RT ARAM Compiler

MH1RT ARAM Compiler Errata

(tamanho do arquivo: 34718, 1 páginas, revisão A, atualizado: 3/09)

MH1RT ARAM Compiler Note

MH1RT

MH1RT Complete

(tamanho do arquivo: 238878, 20 páginas, revisão K, atualizado: 11/07)
Mais documentos...

Gate arrays and embedded arrays fabricated on a radiation hardened 0.35-micron CMOS process, with up to four levels of metal for interconnect. These devices feature arrays of up to 1.6 million routable gates and 596 pads. High density and high pin count capabilities coupled with an ability to embed cores or memories on the same silicon make these arrays one of the best choices for system level integration. These devices are supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Verilog®, DFT®, Synopsys®, and Vital are the reference front end tools. The Cadence® Logic Design Planner associated with timing driven layout provides an efficient back end cycle.

Principais parâmetros

Parâmetro
Valor

Temp. Range (deg C):

-55 to 125

Operating Voltage (Vcc):

3 and 5