Description:

Performs the logical EOR between the contents of register Rd and register Rr and places the result in the destination register Rd.

Operation:

Rd ← Rd ⊕ Rr

Syntax: Operands: Program Counter:

EOR Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1

16-bit Opcode:

0010

01rd

dddd

rrrr

Status Register (SREG) and Boolean Formula:

I

T

H

S

V

N

Z

C

-

-

-

0

-

S: N ⊕ V, For signed tests.

V:0

Cleared

N:R7

Set if MSB of the result is set; cleared otherwise.

Z:

Set if the result is $00; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

eor r4,r4 ; Clear r4
eor r0,r22 ; Bitwise exclusive or between r0 and r22

Words: 1 (2 bytes)

Cycles: 1