### Description:

Rd |
Rr |
R1 |
R0 | ||
---|---|---|---|---|---|

Multiplicand |
× |
Multiplier |
-> |
Product High |
Product Low |

8 |
8 |
16 |

R1:R0 ← Rd × Rr(signed (1.15) ← signed (1.7) × unsigned (1.7))

Syntax: Operands: Program Counter:

FMULSU Rd,Rr 16 ≤ d ≤ 23, 16≤ r ≤ 23 PC ← PC + 1

0000 |
0011 |
1ddd |
1rrr |

### Status Register (SREG) and Boolean Formulae:

I |
T |
H |
S |
V |
N |
Z |
C |
---|---|---|---|---|---|---|---|

- |
- |
- |
- |
- |
- |
⇔ |
⇔ |

Set if bit 15 of the result before left shift is set; cleared otherwise.

Set if the result is $0000; cleared otherwise.

R (Result) equals R1,R0 after the operation.

;****************************************************************************** ;* DESCRIPTION ;*Signed fractional multiply of two 16-bit numbers with 32-bit result. ;* USAGE ;*r19:r18:r17:r16 = ( r23:r22 * r21:r20 ) << 1 ;****************************************************************************** fmuls16x16_32: clr r2 fmuls r23, r21 ;((signed)ah * (signed)bh) << 1 movw r19:r18, r1:r0 fmul r22, r20 ;(al * bl) << 1 adc r18, r2 movw r17:r16, r1:r0 fmulsu r23, r20 ;((signed)ah * bl) << 1 sbc r19, r2 add r17, r0 adc r18, r1 adc r19, r2 fmulsu r21, r22;((signed)bh * al) << 1 sbc r19, r2 add r17, r0 adc r18, r1 adc r19, r2