Mnemonic Operands Description Operation Flags Cycles

LSL

Rd

Logical shift leftRd(n+1)=Rd(n), Rd(0)=0, C=Rd(7)Z,C,N,V,H,S1

LSR

Rd

Logical shift rightRd(n)=Rd(n+1), Rd(7)=0, C=Rd(0)Z,C,N,V,S1

ROL

Rd

Rotate left through carryRd(0)=C, Rd(n+1)=Rd(n), C=Rd(7)Z,C,N,V,H,S1

OR

Rd

Rotate right through carryRd(7)=C, Rd(n)=Rd(n+1), C=Rd(0)Z,C,N,V,S1

ASR

Rd

Arithmetic shift rightRd(n)=Rd(n+1), n=0,...,6Z,C,N,V,S1

SWAP

Rd

Swap nibblesRd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0)None1

BSET

s

Set flagSREG(s) = 1SREG(s)1

BCLR

s

Clear flagSREG(s) = 0SREG(s)1

SBI

P,b

Set bit in I/O registerI/O(P,b) = 1None2

CBI

P,b

Clear bit in I/O registerI/O(P,b) = 0None2

BST

Rr,b

Bit store from register to TT = Rr(b)T1

BLD

Rd,b

Bit load from register to TRd(b) = TNone1

SEC

NoneSet carry flagC =1C1

CLC

NoneClear carry flagC = 0C1

SEN

NoneSet negative flagN = 1N1

CLN

NoneClear negative flagN = 0N1

SEZ

NoneSet zero flagZ = 1Z1

CLZ

NoneClear zero flagZ = 0Z1

SEI

NoneSet interrupt flagI = 1I1

CLI

NoneClear interrupt flagI = 0I1

SES

NoneSet signed flagS = 1S1

CLN

NoneClear signed flagS = 0S1

SEV

NoneSet overflow flagV = 1V1

CLV

NoneClear overflow flagV = 0V1

SET

NoneSet T-flagT = 1T1

CLT

NoneClear T-flagT = 0T1

SEH

NoneSet half carry flagH = 1H1

CLH

NoneClear half carry flagH = 0H1

NOP

NoneNo operationNoneNone1

SLEEP

NoneSleepSee instruction manualNone1

WDR

NoneWatchdog ResetSee instruction manualNone1

BREAK

NoneExecution BreakSee instruction manualNone1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file

Rr: Source register in the register file

b: Constant (0-7), can be a constant expression

s: Constant (0-7), can be a constant expression

P: Constant (0-31/63), can be a constant expression

K6; Constant (0-63), can be a constant expression

K8: Constant (0-255), can be a constant expression

k: Constant, value range depending on instruction. Can be a constant expression

q: Constant (0-63), can be a constant expression

Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions

X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)