入门指南

为您提供开始评估和使用此产品之前所需了解的全部信息。

SPLD and CPLD


Datasheet

PDF

软件

说明

AT22LV10(L)

AT22LV10(L) Datasheet Mature

(12 页数, 更新时间: 08/1999)

500 gate low voltage PLD, standard & low power, 24 pins

更多文档...
Mature product, not recommended for new designs. Low-voltage high-performance programmable logic device (PLD) supports speeds down to 20 ns and power dissipation as low as 14ns. All speed ranges are specified over the 3.0V to 5.5V range. All pins offer a low ±10 μA leakage. The device provides the optimum low-power CMOS PLD solution, with low DC power (1 mA typical at VCC = 3.3V) and full CMOS output levels. It significantly reduces total system power for more effficient battery-powered operations.

关键参数

参数

Operating Voltage (Vcc):

3.3

I/O Pins:

24/28

Commercial tpd:

25

Macrocells:

10

Power Options:

LOW

Registers:

10

Usable Gates:

350