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AT40K05/10/20/40AL

AT40K05/10/20/40AL Summary

(文件大小: 119KB, 4 页数, 修订版 GS, 更新时间: 09/2013)

5K - 50K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam, Enhanced Performance Improvement and Bi-directional I/Os (3.3 V).

AT40K05/10/20/40AL

AT40K05/10/20/40AL Complete

(文件大小: 1.14MB, 51 页数, 修订版 G, 更新时间: 09/2013)

5K - 50K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam, Enhanced Performance Improvement and Bi-directional I/Os (3.3 V).

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This 5,000 to 10,000-gate fully PCI-compliant, SRAM-based FPGA features distributed 10-ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic® ability (partially or fully reconfigurable without loss of data), and automatic component generators. It has a 128 I/O count and supports 3.3-V designs. This FPGA can be used as a coprocessor for high-speed (DSP/processor-based) designs by implementing a variety of computation intensive, arithmetic functions. It is designed to quickly implement high-performance, large gate count designs through the use of synthesis and schematic-based tools used on a PC or Sun platform.

关键参数

参数

F.max (MHz):

100 MHz

Max. Operating Freq. (MHz):

100 MHz

Max I/O Pins:

128

Operating Voltage (Vcc):

3.3

Speed:

-1

Registers:

496

Usable Gates:

5K - 10K

Memory:

2048