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Datasheet

PDF

软件

说明

AT40K05/10/20/40

AT40K05/10/20/40 Complete

(文件大小: 1.27MB, 55 页数, 修订版 E, 更新时间: 06/2013)

5K - 50K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam. (LV are mature)

AT40K05/10/20/40(LV)

AT40K05/10/20/40(LV) Datasheet Mature

(4 页数, 更新时间: 05/2002)

5K - 50K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam.

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Mature product, not recommended for new designs. Replacement device: AT40K10AL and the AT40KxxAL products. This 10,000 to 20,000-gate coprocessor is a fully PCI-compliant, SRAM-based FPGA with distributed 10-ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic® ability (partially or fully reconfigurable without loss of data), and automatic component generators. It has a 192 I/O count and supports a 3.3-V design. It can be used as a coprocessor for high-speed (DSP/processor-based) designs by implementing a variety of computation intensive, arithmetic functions. It is designed to quickly implement high-performance, large gate count designs through the use of synthesis and schematic-based tools used on a PC or Sun platform.

关键参数

参数

F.max (MHz):

250 MHz

Max. Operating Freq. (MHz):

250 MHz

Max I/O Pins:

192

Operating Voltage (Vcc):

3.3

Speed:

-3

Registers:

576

Usable Gates:

10K - 20K

Memory:

4608