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Datasheet

PDF

软件

说明

ATU18

ATU18 Datasheet

(文件大小: 191479, 12 页数, 修订版 C, 更新时间: 08/2005)
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The ATU18 series of ULCs are fully suited for conversion of latest CPLDs and FPGAs. It supports within one ULC with 55Kbits to 847Kbits DPRAM and 45K to 1000K gates. Typically, the ULC die size is 50 percent smaller than the equivalent FPGA and requires significantly less operatingpower. Metal-level customization allows a DPRAM blocks compatibility with XiLINx® or Altera® blocks.

关键参数

参数

Temp. Range (deg C):

-55 to 125

Max. Operating Freq. (MHz):

400 MHz